With DP 2.1 in the current gen of AMD cards, is there any word of a DP 2.1 to HDMI 2.1 adapter? I believe the amount of bandwidth in DP 2.1 would allow for a great experience in Linux, where native HDMI 2.1 is not supported above 4k 60hz
DP 2.1 to HDMI 2.1 adapter
Updated on 16-01-2023 in
DisplayPort 1.4 to 4K120Hz HDMI Adapter
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DP 2.1 is not very specific it could be 40Gbps or 80 Gbps. Where 40Gbps is below the 48Gbps of HDMI 2.1. I think they might be looking in to cables first, determine the “standard” and built from there. I mean, have you seen a VESA certified DP2.1 cable yet?
I think it’s to early to assume there will be any DP2.1 to HDMI 2.1 adapters soon.
But have you tried the CAC-1085? That can do 4K120Hz over HDMI. But not sure if it will work on an AMD card + Linux.
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Right, DP 2.1 can be 40, 54, 80 Gbps (38.685, 52.22475, 77.37 Gbps for data).
But HDMI 2.1 is also not specific. It could be 24, 32, 40, 48 Gbps (21.33, 28.44, 35.55, 42.66 Gbps for data)
Any Thunderbolt 4 or USB4 cable should be able to do DP 2.1 at 80 Gbps since it’s just 4 lanes at 20 Gbps each. Are there any USB-C ports that can do DP 2.1? I think current GPUs that support DP 2.1 don’t do the max 80 Gbps yet anyway.
DP 1.4 max is 32.4 Gbps (25.92 Gbps). It does ≈60% the bandwidth of HDMI 2.1 so it’s not bad. Plus, DSC can more than triple the pixel clock by reducing bpp from 30 to 12 bpp, so HBR3 can do 2160 MHz which is good enough for 8K60 CVT-RB but not good enough for 8K60 HDMI. DSC can maybe go as low as 8bpp though (but I haven’t seen it or tried it), which would allow a pixel clock of 3240 MHz.
I’m not sure why the CAC-1085 is limited to 4K120 (8K30) instead of 4K240 (8K60) since DisplayPort 1.4 can do that with DSC using CVT-RB timings. I’ve never tried the CAC-1085 with a display that can do that pixel clock. I don’t think there are any displays that can do 4K240? I have a Dr HDMI 8K which might be able to fake such a display but I’m not sure if it does 48 Gbps (FRL-6).
Below is the DisplayPort DPCD info from the CAC-1085 while doing 4K120 4:2:0 10bpc from macOS Ventura running on Mac mini 2018 with Radeon Pro W5700 eGPU. I don’t think macOS enables DSC or 4:4:4 or RGB by default with DisplayPort to HDMI 2.1 adapters. The info says the CAC-1085 can do 48 Gbps though. I’ll have to try doing some macOS patches and using an 8K60 or 4K240 EDID to find the real limits.
00000h: 12 14 c4 81 01 1d 01 84 00 00 04 00 00 00 84 00 // ................ 00060h: 03 21 00 02 2b 04 01 00 00 1f 0e 11 08 00 00 00 // .!..+........... 00080h: 0b f0 1a 1e 5f 00 00 00 5f 00 00 00 5f 00 00 00 // ...._..._..._... 00090h: bf 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 00100h: 1e 84 00 02 02 02 02 10 01 00 00 00 00 00 00 00 // ................ 00200h: 41 04 77 77 01 00 22 22 00 00 00 00 00 00 00 00 // A.ww..""........ 00210h: 00 80 00 80 00 80 00 80 00 00 00 00 00 00 00 00 // ................ 00240h: 00 00 00 00 00 00 20 00 00 00 00 00 00 00 00 00 // ...... ......... 00280h: 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 00300h: 00 10 fa 41 41 50 4c 00 00 01 01 00 00 00 00 00 // ...AAPL......... 00310h: 00 10 fa 70 48 44 4d 49 67 10 01 00 01 04 20 01 // ...pHDMIg..... . 00500h: 00 e0 4c 44 70 31 2e 34 00 20 82 00 00 00 00 00 // ..LDp1.4. ...... 00510h: 28 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // (............... 00600h: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 02000h: 00 00 41 04 00 00 00 00 00 00 00 00 77 77 01 00 // ..A.........ww.. 02200h: 14 1e c4 81 01 1d 01 84 00 00 04 00 00 00 84 00 // ................ 02210h: 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 03000h: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 // ................ 03030h: 00 00 00 00 03 00 21 00 00 00 00 01 00 00 00 00 // ......!......... Receiver Capability 00000h DPCD_REV: 1.2 00001h MAX_LINK_RATE: HBR2 00002h MAX_LANE_COUNT: 4, ENHANCED_FRAME_CAP, TPS3_SUPPORTED 00003h MAX_DOWNSPREAD: MAX_DOWNSPREAD_0_5, TPS4_SUPPORTED 00004h NORP: 2 00005h DOWNSTREAMPORT_PRESENT: DWN_STRM_PORT_PRESENT, PORT_TYPE = DVI or HDMI, FORMAT_CONVERSION, DETAILED_CAP_INFO_AVAILABLE 00006h MAIN_LINK_CHANNEL_CODING: CAP_ANSI_8B10B 00007h DOWN_STREAM_PORT_COUNT: 4, OUI_SUPPORT 0000ah RECEIVE_PORT_1_CAP_0: ASSOCIATED_TO_PRECEDING_PORT 0000eh TRAINING_AUX_RD_INTERVAL: 16ms all, EXTENDED_RECEIVER_CAP_FIELD_PRESENT 00060h DSC_SUPPORT: DSC_DECOMPRESSION_IS_SUPPORTED, ?0x02 00061h DSC_REV: 1.2 00062h DSC_RC_BUF_BLK_SIZE: 1kB 00063h DSC_RC_BUF_SIZE: 2 * DSC_RC_BUF_BLK_SIZE 00064h DSC_SLICE_CAP_1 & 2: 1, 2, 4, 8 max slices per DisplayPort DSC sink 00065h DSC_LINE_BUF_BIT_DEPTH: 13 bits 00066h DSC_BLK_PREDICTION_SUPPORT: DSC_BLK_PREDICTION_IS_SUPPORTED 00067h DSC_MAX_BITS_PER_PIXEL: 0 bpp 00069h DSC_DEC_COLOR_FORMAT_CAP: RGB, YCbCr 4:4:4, YCbCr 4:2:2 Simple, YCbCr 4:2:2 Native, YCbCr 4:2:0 Native 0006ah DSC_DEC_COLOR_DEPTH_CAP: 8, 10, 12 bpc 0006bh DSC_PEAK_THROUGHPUT: MODE_0 = 340 Mp/s, MODE_1 = 340 Mp/s 0006ch DSC_MAX_SLICE_WIDTH: 2560 pixels 0006fh DSC_BITS_PER_PIXEL_INC: 1/16 bpp 00080h DOWNSTREAM_PORT_0: PORT_TYPE = HDMI, HPD aware, 600 MHz max TMDS clock, DS_MAX_BPC = 12bpc, PCON_MAX_FRL_BW = 48Gbps, YCBCR422_PASS_THROUGH, YCBCR420_PASS_THROUGH, YCBCR444_TO_422_CONV, YCBCR444_TO_420_CONV 00084h DOWNSTREAM_PORT_1: PORT_TYPE = ?7 (reserved), HPD aware, ?0x50 00088h DOWNSTREAM_PORT_2: PORT_TYPE = ?7 (reserved), HPD aware, ?0x50 0008ch DOWNSTREAM_PORT_3: PORT_TYPE = ?7 (reserved), HPD aware, ?0x50 00090h FEC_CAPABILITY: FEC_CAPABLE, FEC_UNCORR_BLK_ERROR_COUNT_CAP, FEC_CORR_BLK_ERROR_COUNT_CAP, FEC_BIT_ERROR_COUNT_CAP, PARITY_BLOCK_ERROR_COUNT_CAP, PARITY_ERROR_COUNT_CAP, FEC_ERROR_REPORTING_POLICY_SUPPORTED Link Configuration 00100h LINK_BW_SET: HBR3 00101h LANE_COUNT_SET: 4, ENHANCED_FRAME_EN 00103h TRAINING_LANE0_SET: TRAIN_VOLTAGE_SWING_LEVEL_2, TRAIN_PRE_EMPH_LEVEL_0 00104h TRAINING_LANE1_SET: TRAIN_VOLTAGE_SWING_LEVEL_2, TRAIN_PRE_EMPH_LEVEL_0 00105h TRAINING_LANE2_SET: TRAIN_VOLTAGE_SWING_LEVEL_2, TRAIN_PRE_EMPH_LEVEL_0 00106h TRAINING_LANE3_SET: TRAIN_VOLTAGE_SWING_LEVEL_2, TRAIN_PRE_EMPH_LEVEL_0 00107h DOWNSPREAD_CTRL: SPREAD_AMP_0_5 00108h MAIN_LINK_CHANNEL_CODING_SET: SET_ANSI_8B10B 00160h DSC_ENABLE: disabled Link/Sink Device Status 00200h SINK_COUNT: 1, SINK_CP_READY 00201h DEVICE_SERVICE_IRQ_VECTOR: CP_IRQ 00202h LANE0_1_STATUS: LANE0 = CR_DONE, CHANNEL_EQ_DONE, SYMBOL_LOCKED 00202h LANE0_1_STATUS: LANE1 = CR_DONE, CHANNEL_EQ_DONE, SYMBOL_LOCKED 00203h LANE2_3_STATUS: LANE2 = CR_DONE, CHANNEL_EQ_DONE, SYMBOL_LOCKED 00203h LANE2_3_STATUS: LANE3 = CR_DONE, CHANNEL_EQ_DONE, SYMBOL_LOCKED 00204h LANE_ALIGN_STATUS_UPDATED: INTERLANE_ALIGN_DONE 00206h ADJUST_REQUEST_LANE0_1: LANE0 = ADJUST_VOLTAGE_SWING_LEVEL_2, ADJUST_PRE_EMPHASIS_LEVEL_0 00206h ADJUST_REQUEST_LANE0_1: LANE1 = ADJUST_VOLTAGE_SWING_LEVEL_2, ADJUST_PRE_EMPHASIS_LEVEL_0 00207h ADJUST_REQUEST_LANE2_3: LANE2 = ADJUST_VOLTAGE_SWING_LEVEL_2, ADJUST_PRE_EMPHASIS_LEVEL_0 00207h ADJUST_REQUEST_LANE2_3: LANE3 = ADJUST_VOLTAGE_SWING_LEVEL_2, ADJUST_PRE_EMPHASIS_LEVEL_0 00210h SYMBOL_ERROR_COUNT_LANE0: 0, valid 00212h SYMBOL_ERROR_COUNT_LANE1: 0, valid 00214h SYMBOL_ERROR_COUNT_LANE2: 0, valid 00216h SYMBOL_ERROR_COUNT_LANE3: 0, valid 00246h TEST_SINK_MISC: TST_CRC_COUNT = 0, TEST_CRC_SUPPORTED 00282h FAUX_BACK_CHANNEL_SYMBOL_ERROR_COUNT_CONTROL: COUNT_SYMBOL Source Device-Specific 00300h SOURCE_OUI: 00-10-FA = Apple, Inc. 00303h SOURCE_ID: 41 41 50 4c 00 00 // AAPL.. 00309h SOURCE_HW_REV: 0.1 0030ah SOURCE_SW_REV: 1.0 00310h : 00 10 fa 70 48 44 4d 49 67 10 01 00 01 04 20 01 // ...pHDMIg..... . Branch Device-Specific 00500h BRANCH_OUI: 00-E0-4C = REALTEK SEMICONDUCTOR CORP. 00503h BRANCH_ID: 44 70 31 2e 34 00 // Dp1.4. 00509h BRANCH_HW_REV: 2.0 0050ah BRANCH_SW_REV: 130.0 00510h : 28 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // (............... Sink Control 00600h SET_POWER: SET_POWER_D0 DPRX ESI (Event Status Indicator) 02002h SINK_COUNT_ESI: 1, SINK_CP_READY 02003h DEVICE_SERVICE_IRQ_VECTOR_ESI0: CP_IRQ 0200ch LANE0_1_STATUS_ESI: LANE0 = CR_DONE, CHANNEL_EQ_DONE, SYMBOL_LOCKED 0200ch LANE0_1_STATUS_ESI: LANE1 = CR_DONE, CHANNEL_EQ_DONE, SYMBOL_LOCKED 0200dh LANE2_3_STATUS_ESI: LANE2 = CR_DONE, CHANNEL_EQ_DONE, SYMBOL_LOCKED 0200dh LANE2_3_STATUS_ESI: LANE3 = CR_DONE, CHANNEL_EQ_DONE, SYMBOL_LOCKED 0200eh LANE_ALIGN_STATUS_UPDATED_ESI: INTERLANE_ALIGN_DONE Extended Receiver Capability 02200h DP13_DPCD_REV: 1.4 02201h MAX_LINK_RATE: HBR3 02202h MAX_LANE_COUNT: 4, ENHANCED_FRAME_CAP, TPS3_SUPPORTED 02203h MAX_DOWNSPREAD: MAX_DOWNSPREAD_0_5, TPS4_SUPPORTED 02204h NORP: 2 02205h DOWNSTREAMPORT_PRESENT: DWN_STRM_PORT_PRESENT, PORT_TYPE = DVI or HDMI, FORMAT_CONVERSION, DETAILED_CAP_INFO_AVAILABLE 02206h MAIN_LINK_CHANNEL_CODING: CAP_ANSI_8B10B 02207h DOWN_STREAM_PORT_COUNT: 4, OUI_SUPPORT 0220ah RECEIVE_PORT_1_CAP_0: ASSOCIATED_TO_PRECEDING_PORT 0220eh TRAINING_AUX_RD_INTERVAL: 16ms all, EXTENDED_RECEIVER_CAP_FIELD_PRESENT 02210h DPRX_FEATURE_ENUMERATION_LIST: SST_SPLIT_SDP_CAP, VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED PCON HDMI CONFIG PPS Override Buffer 0300fh CEC_LOGICAL_ADDRESS_MASK_2: CEC_LOGICAL_ADDRESS_15 03030h : 00 00 00 00 03 00 // ...... 03036h PCON_HDMI_POST_FRL_STATUS: PCON_HDMI_LINK_MODE = PCON_HDMI_MODE_FRL, PCON_HDMI_FRL_TRAINED_BW = 40Gbps 0303bh PCON_HDMI_TX_LINK_STATUS: PCON_HDMI_TX_LINK_ACTIVE
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